Verification Enhancement through Reasoning Agents
A four-agent AI framework that automates semiconductor design verification —
from specification parsing to coverage closure to hardware security validation.
Modern processors contain tens of billions of transistors. Proving they work correctly before manufacturing consumes the majority of engineering time — and current tools haven't fundamentally changed in two decades.
Reaching 95%+ functional coverage on a complex IP block takes 3–8 weeks of iterative constraint tuning. Engineers re-discover the same coverage gaps design cycle after design cycle.
UVM testbench components — sequences, scoreboards, coverage groups — are largely written from scratch. A single complex IP verification effort can require 100,000+ lines of testbench code.
When a simulation fails, isolating the root cause takes 4–40 hours of a senior engineer's time per failure. At scale, this bottleneck alone can stall a tapeout schedule by weeks.
Hardware Trojans, privilege escalation, and side-channel vulnerabilities are manually checked — if at all. No systematic AI tooling exists for RTL-level hardware security verification.
VERA is a modular AI platform where four specialized agents share a persistent Verification Knowledge Graph (VKG), enabling institutional learning across design cycles for the first time.
Ingests natural-language specs, RTL source, and existing plans. Produces structured, machine-readable verification intent with full requirement traceability, including implicit security constraints.
Generates syntactically correct, executable UVM testbench components and SVA security property checkers from verification intent. Iterative self-correction loop handles compiler errors automatically.
The core RL subsystem. Continuously analyzes coverage database state during simulation and adaptively generates test stimuli to close functional and security coverage gaps. Replaces manual constraint tuning.
Activates on simulation failures. Classifies bug type, distinguishes functional bugs from hardware security violations, and proposes root-cause corrections. Hardware Trojan indicator detection included.
All four agents share a persistent, versioned knowledge graph spanning design intent, coverage state, simulation history, security properties, and bug records. The VKG enables institutional learning that current DV environments cannot provide — knowledge compounds across design cycles.
Every VERA target is benchmarked against current industry practice on the CVA6 open-source RISC-V processor — a production-quality design representative of commercial IP verification challenges.
| GENESIS CHALLENGE | VERA CONTRIBUTION |
|---|---|
| AI-Driven Autonomous Laboratories | VERA automates the full DV workflow end-to-end, enabling research teams to execute orders of magnitude more simulation experiments with minimal manual intervention — the definition of an autonomous scientific laboratory for chip design. |
| Semiconductors & Microelectronics | Primary focus: VERA directly addresses the dominant productivity bottleneck in U.S. semiconductor design programs, with an explicit hardware security verification extension that no existing AI tool provides. |
| National Security (NNSA) | Hardware security validation capabilities address NNSA requirements for verified, Trojan-free chip designs used in national security systems. The security assertion library will be released as an open DOE platform resource. |
| Advanced Manufacturing | Faster, more thorough DV reduces tape-out failures and re-spins, directly improving yield and competitiveness in domestic semiconductor manufacturing programs supported by CHIPS Act investment. |
VERA is seeking a university partner with active semiconductor or EDA research infrastructure.
Phase I awards range from $500K–$750K over 9 months (DE-FOA-0003612).